To ensure proper functionality and reliability, manufacturers typically test SOC integrated circuits (ICs) before shipping SOC ICs to customers. One system commonly employed to test SOC ICs is the Agilent 93000 SOC Tester, which supports concurrent tests. Portions of the Agilent 93000 SOC Tester are described in U.S. Pat. No. 6,756,778 to Hirschmann entitled “Measuring and/or calibrating a Test Head;” U.S. Pat. No. 5,558,541 to Botka et al. entitled “Blind Mate Connector for an Electronic Circuit Tester;” and U.S. Pat. No. 5,552,701 to Veteran et al. entitled “Docking System for an Electronic Circuit Tester.”
As illustrated in FIGS. 1 and 2, Agilent 93000 Tester 100 comprises test head 110 with DUT (Device under test) interface 120, manipulator 130 for positioning test head 110, DUT board 150 which plugs into underlying DUT interface 120, support rack 140 for supplying test head 110 with electrical power, cooling water and compressed air (not shown in the Figures) and a computer workstation (not shown in the Figures) which serves as the user interface to Tester 100.
Test head 110 comprises tester electronics and additional analog modules. In past, test head 110 has been configured with 512 pins or 1024 pins. The 512 pin test head supports 4 card cages while the 1024 pin test head supports 8 card cages. Each card cage can contain 8 digital boards or 8 analog modules, respectively. A single board has 16 pins, making 128 pins per cage. Therefore, the 4-cage test head contains 512 pins and the 8-cage test head 1024 pins. The DUT is mounted on DUT board 150, which is connected to the I/O channels by DUT interface 120. DUT interface 120 consists of high performance coax cabling and spring contact pins (pogo pins) which establish electrical connection with DUT board 120.
DUT interface 120 provides docking capabilities to handlers and wafer probers. The docking mechanism is controlled by compressed air (not shown in the Figures), and if required may also be operated manually. Test head 110 is water-cooled and receives its cooling water supply from support rack 140, which in turn is connected by two flexible hoses to the cooling unit (not shown in the Figures).
General-purpose manipulator 130 supports and positions test head 110. Manipulator 130 provides 6 degrees of freedom for precise and repeatable connections between test head 100 and handlers or wafer probers. Support rack 140 is attached to manipulator 130 and serves as the interface between test head 110 and AC power, cooling water and compressed air. Tester 100 may also comprise additional support racks such as analog support racks for installing additional analog instruments.
An HP-UX workstation (not shown in the Figures) may serve as the interface between the user and tester 100. At the present time, Agilent 93000 SOC Series SmarTest software runs on the HP-UX workstation under the HP-UX operating system, although other suitable operating systems such as Linux or other workstations may certainly be used. SmarTest allows setups and test data to be downloaded to the test system, and further permits editing of such information. All testing is carried out in the test system. Results are read back by the workstation and displayed on the monitor. During test program execution, upload and download are typically not required since the test processors act independently from the workstation once the test program has begun running.
On the workstation, a diagnostic program can be run to check the system periodically or to identify the source of a problem. Configuration of Tester 100 involves assigning digital channel boards, power supplies, and analog instruments to specific channels of the test head and providing for associated mainframe components (such as an alternate master clock (AMC)) external to the test head.
Test head electronics components supply power to the various DUTs and perform measurements. Some test head functions and key elements are as follows:                DC/DC conversion and distribution of supply voltages        Interfacing via fiber optical cable to the workstation        Internal communication via data bus, address bus, and control bus        Communication clock generation and distribution        Master clock generation and distribution        High precision parametric measurement unit (HPPMU)        Interfacing to external clock        Supplying power to the DUT        Making channel measurements        
Such flexibility in Tester 100 allows for on-the-fly grouping of pins into virtual ports to test target IP blocks. As a result, the platform is capable of testing multiple blocks concurrently. Once a test has been completed, tester pins may be immediately reconfigured and assembled into new port configurations to conduct a completely different set of tests.
The architecture of Tester 100 provides support for concurrent tests on potentially dozens of ports with different sequencing and digital data rates. The test-processor-per-pin architecture of Tester 100 allows it to function as a scalable platform. Tester 100 supports test technologies that include RF, analog, digital and mixed signal, each fully capable of being used concurrently.
FIG. 2 illustrates the placing of DUT 160 on packaged parts DUT board 150, and the positioning of DUT board 150 above test head 110.
One of the most expensive components of manufacturing an integrated circuit or chip is “cost of test.” Consequently, increasing the throughput of Tester 100 becomes imperative in reducing cost. Increasing throughput in an economic manner has proven easier said than done, however. To date, the principal methods employed to utilize tester 100's resources efficiently and cost-effectively have been: (a) parallel test; (b) concurrent test and (c) strip test.
Parallel test methods permit multiple DUTs to be tested simultaneously, typically on four different sites. The biggest problem characterizing parallel test techniques is that sufficient resources must be available to operate simultaneously all sites, and that at any given moment during testing most resources are not being actively utilized. Consequently, the time to test a chip is the amount of time required to run a full test plan. A performance increase of “num sites×time of complete test-plan” results.
Concurrent test methods permit several tests to be performed on a DUT simultaneously. DUTs amenable to concurrent test methods, however, usually must be designed with concurrent tests in mind. Resources are usually better utilized in concurrent tests than in Parallel tests, and can result in significantly shortened test times. Several drawbacks to concurrent test methods exist: Not all tests may be run concurrently; concurrent testing requires greater up-front investment in equipment to design DUTs amenable to concurrent testing; many chip diagrams generally do not lend themselves to “design for concurrent test;” and “designing for concurrent test” may lead to less-than-optimal chip design.
Strip test methods do not involve using tester resources in some superior fashion, but in using a handler more efficiently through reducing index handler time. The distance a handler moves between DUTs mounted on a strip is minimal while between strips handler index time remains constant. In strip testing, some preprocessing and post handler processing of DUTs is required. Strip test methods require DUT binning that must be done after testing has been completed. Much information must also be processed to properly bin tested DUTs.
In summary, a review of current test options shows that parallel test methods are capable of testing DUTs at a rate up to about four times that of conventional methods but require quite complex systems; strip test methods merely reduce handler index times; and concurrent test methods have hidden design costs and other tradeoffs.
What is needed is an improved method of testing SOCs that results in faster testing at lower cost, where the improved method can function in combination with older testers, other equipment and methods.